1. Field of the Invention
The present invention relates to a frequency synthesizer apparatus equipped with a fraction part control circuit, a communication apparatus, a frequency modulator apparatus, and a frequency modulating method each utilizing the frequency synthesizer apparatus. In particular, the present invention relates to a frequency synthesizer apparatus comprising a phase-locked loop circuit (hereinafter referred to as a PLL circuit) and a fraction part control circuit, which utilizes the PLL circuit to control a fraction part of a number of frequency division inputted to a variable frequency divider provided in the PLL circuit, a communication apparatus, a frequency modulator apparatus, and a frequency modulating method each utilizing the frequency synthesizer apparatus.
2. Description of the Related Art
Generally speaking, an output frequency of a frequency synthesizer apparatus using a PLL circuit is expressed by a quotient that is calculated by dividing a reference signal frequency by a number of frequency division set in a variable frequency divider. Since a general variable frequency divider can set only the number of frequency division as integer data, the output frequency is equal to an integral multiple of the frequency of the reference signal, and thus, the output frequency cannot be set to a unit that is smaller than the frequency of the reference signal. Therefore, the frequency of the reference signal must be lowered when it is necessary to set the output frequency at shorter frequency intervals. However, the lower reference signal frequency causes a larger number of frequency division of the variable frequency divider, and noise occurring in an output signal also increases as the number of frequency division increases. Since a response bandwidth of the PLL circuit cannot be wider than that of the frequency of the reference signal, a response speed of a loop of the PLL circuit decreases, and this leads to the period of switching over between frequencies to increase.
A method for obtaining a number of frequency division having decimal precision by using a general variable frequency divider has been known as a method for solving the above-mentioned problems. This method is provided for realizing a number of frequency division having a decimal precision as average data by periodically changing the number of frequency division. This method utilizes a delta-sigma modulator circuit (or a xcex94-xcexa3 modulator circuit: sometimes called a sigma-delta modulator circuit (or a xcex94-xcexa3 modulator circuit)).
FIG. 19 is a block diagram showing a circuit configuration of a frequency synthesizer apparatus of the prior art. The frequency synthesizer apparatus is provided for realizing a number of frequency division having decimal precision.
Referring to FIG. 19, the frequency synthesizer apparatus comprises a voltage control oscillator 1 (hereinafter referred to as a VCO), a variable frequency divider 2 (or frequency demultiplier), a phase comparator 3, and a low-pass filter 4 including a loop filter, which are connected in a loop configuration. The frequency synthesizer apparatus further comprises a fraction part control circuit 80 and an adder 6. The variable frequency divider 2 divides the frequency of an output signal from the VCO 1 in accordance with input data of a number of frequency division, and then outputs the frequency-divided signal to the phase comparator 3. The phase comparator 3 performs a phase comparison between an input reference signal and the output signal from the variable frequency divider 2, and then outputs a signal indicating the result of phase comparison to the VCO 1 through the low-pass filter 4. Thus, a PLL circuit is feedback-controlled so as to stabilize the output frequency of the VCO 1.
Referring to FIG. 19 again, the fraction part control circuit 80 comprises an adder 81 and a delay circuit 82. The adder 81 adds data of a fraction part F inputted from an external apparatus to output data from the delay circuit 82, and then outputs the resultant addition data to the delay circuit 82. The delay circuit 82 is a latch circuit which operates by using the output signal from the variable frequency divider 2 as a clock. The adder 6 adds an output signal indicating an overflow of the adder 81, i.e., a carry signal (indicating data of the controlled fraction part F), to data of an integral part M inputted from the external apparatus, and then inputs and sets resultant addition data as data of a number of frequency division in the variable frequency divider 2.
In the frequency synthesizer apparatus of FIG. 19 configured as described above, when a fraction part is equal to F, data of the output signal from the adder 81 increases by the fraction part F every clock period. When the adder 81 overflows as a result of a data L, the adder 81 overflows F times for a period of L clocks, and generates the carry signal.
FIG. 20 is a block diagram of a detailed configuration of the fraction part control circuit 80 shown in FIG. 19, showing the configuration using a z-transformation. In FIG. 20, zxe2x88x921  represents the delay of one clock. Output data Y from the fraction part control circuit 80 is expressed by the following Equation (1).
Y=F/L+(1xe2x88x92zxe2x88x921)Qxe2x80x83xe2x80x83(1)
An operation of the fraction part control circuit 80 is equivalent to that of a first-order delta-sigma modulator circuit. Generation of the carry signal is equivalent to quantization using a quantization step L.
Referring to FIG. 20, the fraction part control circuit 80 comprises an adder 91, a delay circuit 92, a quantizer 93, a multiplier 94 and a subtracter 95. The adder 91 corresponds to the adder 81 shown in FIG. 19. The delay circuit 92 corresponds to the delay circuit 82 shown in FIG. 19. The subtracter 95 subtracts output data from the multiplier 94 from data of the fraction part F inputted from the external apparatus, and then outputs resultant subtraction data to the adder 91. The adder 91 adds an output signal from the delay circuit 92 to an output signal from the subtracter 95, and then outputs the result of addition to the delay circuit 92 and the quantizer 93. The quantizer 93 quantizes an output signal from the adder 91 using the quantization step L, and then outputs the quantized signal. The multiplier 94 multiplies the output signal from the quantizer 93,by the quantization step L, and then outputs a resultant multiplication signal to the subtracter 95.
FIG. 21 shows timing charts of an operation of the frequency synthesizer apparatus shown in FIG. 19, where FIG. 21(a) is a timing chart showing a change over time in a number of frequency division inputted to the variable frequency divider 2, and FIG. 21(b) is a timing chart showing a change over time in a control voltage to the VCO 1.
As is apparent from FIG. 21(a), the data corresponding to a number of frequency division is equal to M when no carry signal is generated, and the data of a number of frequency division is equal to M+1 when a carry signal is generated. Accordingly, average data is equal to (M+F/L) during L clock periods. Therefore, an output frequency of the VCO 1 is equal to an (M+F/L) multiple ((M+F/L)-fold or (M+F/L) times) of a frequency of a reference signal. Thus, the data of the fraction part F is changed, and this leads to the output frequency of the VCO 1 being set to an output frequency at an interval of 1/L of the frequency of the reference signal.
In the frequency synthesizer apparatus which utilizes the delta-sigma modulator circuit of the prior art to realize an output frequency equaling a non-integral multiple of a reference signal frequency with decimal precision, the data of a number of frequency division periodically changes at an interval of a basic period of L clocks (a changing period xcex94P) as shown in FIG. 21(a). As shown in FIG. 21(b), an output signal of the phase comparator 3 varies according to the above-mentioned change. Thus, a spectrum of the control voltage to the VCO 1 changes as shown in FIG. 23. At this time, an output of the VCO 1 is frequency-modulated, and thus the spectrum thereof changes as shown in FIG. 22.
As is apparent from FIG. 22, the spectrum of the output signal from the VCO 1 has high spurious components, i.e., a double side band signal having both side bands located at frequencies shifted upward and downward from a reference frequency by a changing frequency xcex94f corresponding to the above-mentioned changing period xcex94P. When data of the fraction part F is small, this would cause a variation of low-frequency components of and a high spurious level. It is therefore difficult for the low-pass filter 4 to sufficiently reduce the spurious level.
An essential object of the present invention is to provide a frequency synthesizer apparatus which is capable of realizing an output frequency which is equal to a non-integral multiple of a reference signal frequency with decimal precision, and which is capable of reducing spurious components.
Another object of the present invention is to provide a communication apparatus and a frequency modulator apparatus using the above-mentioned frequency synthesizer apparatus.
A further object of the present invention is to provide a frequency modulating method using the above-mentioned frequency synthesizer apparatus.
According to one aspect of the present invention, there is provided a frequency synthesizer apparatus comprising:
a voltage control oscillator for generating an output signal having a frequency corresponding to an input control voltage;
a variable frequency divider for dividing the frequency of the output signal from the voltage control oscillator in accordance with an input data corresponding to a number of frequency division, and for outputting a frequency-divided signal;
a phase comparator for performing a phase comparison between the output signal from the variable frequency divider and an input reference signal, and generating and outputting a signal indicating a result of the phase comparison;
a low-pass filter for low-pass-filtering the signal from the phase comparator, and outputting the low-pass-filtered signal to the voltage control oscillator;
a fraction part control circuit for receiving an input data of a fraction part, for controlling the input data of the fraction part so as to periodically change the input data of the fraction part with a predetermined period and for outputting data of controlled fraction part; and
an adder means for adding an input data of an integral part to the data of the controlled fraction part outputted from the fraction part control circuit, and for outputting resultant addition data to the variable frequency divider as the input data corresponding to a number of frequency division,
wherein the fraction part control circuit is of a plural-n-th-order delta-sigma modulator circuit, the fraction part control circuit comprising:
a plural-n-th-order integrator, having one data input terminal and one data output terminal, for applying plural-n-th-order integration to input data of a fraction part, and outputting plural-n-th-order integrated data through the one data output terminal;
a quantizer for quantizing the data outputted from the one data output terminal of the plural-n-th-order integrator with a predetermined quantization step, and for outputting the quantized data as the data of the controlled fraction part; and
a feedback circuit for feeding back the quantized data from the quantizer together with the input data of the fraction part to the plural-n-th-order integrator, and
wherein the frequency synthesizer apparatus set a frequency of the output signal from the voltage control oscillator in accordance with an average value of the controlled input data of the fraction part of a period.
In the above-mentioned frequency synthesizer apparatus, the quantizer preferably generates data of an integral part of a quotient that is calculated by dividing the data outputted from the plural-n-th-order integrator by the predetermined quantization step, and outputs the generated data as the data of the controlled fraction part, and
wherein the frequency synthesizer apparatus further comprises:
a first multiplier for multiplying data outputted from the feedback circuit by the quantization step, and for outputting resultant multiplication data; and
a first adder for adding the data outputted from the first multiplier, to input data of a fraction part, and for outputting resultant addition data to the plural-n-th-order integrator.
In the above-mentioned frequency synthesizer apparatus, the fraction part control circuit is preferably a binary logic circuit for representing negative numbers in two""s-complement form,
wherein the predetermined quantization step is represented by a power of two,
wherein the quantizer outputs data of higher-order bits indicating data equal to or larger than the quantization step among the quantized data, and
wherein the plural-n-th-order integrator receives a combination of data of higher-order bits composed of the output data from the feedback circuit, and data of lower-order bits composed of the input data of the fraction part.
In the above-mentioned frequency synthesizer apparatus, either one of the reference signal or the output signal from the variable frequency divider is preferably used as a clock,
wherein a transfer function of the plural-n-th-order integrator is expressed by 1/(1xe2x88x92zxe2x88x921)n using a z-transformation representing delay of one clock period as zxe2x88x921, and
wherein a transfer function of the feedback circuit is expressed by (1xe2x88x92zxe2x88x921)nxe2x88x921 using the z-transformation.
In the above-mentioned frequency synthesizer apparatus, the plural-n-th-order integrator preferably comprises a plurality of n first-order integrators which are cascade-connected,
wherein each of the first-order integrators comprises a second adder and a one-clock delay circuit,
wherein the second adder adds data inputted to each of the first-order integrators to output data from the one-clock delay circuit, and outputs resultant addition data as input data to the first-order integrator of the following stage, and
wherein the one-clock delay circuit delays the output data from the second adder by one clock period and outputs the delayed data to the second adder.
In the above-mentioned frequency synthesizer apparatus, the plural-n-th-order integrator preferably comprises:
a second adder; and
a composite delay circuit having a transfer function which is expressed by 1xe2x88x92(1xe2x88x92zxe2x88x921)n using a z-transformation representing delay of one clock as zxe2x88x921, and
wherein the second adder adds data inputted to the plural-n-th-order integrator, to output data from the composite delay circuit, outputs resultant addition data to the composite delay circuit, and outputs the resultant addition data as output data from the plural-n-th-order integrator.
In the above-mentioned frequency synthesizer apparatus, either one of the reference signal or the output signal from the variable frequency divider is preferably used as a clock,
wherein a transfer function of the plural-n-th-order integrator is expressed by zxe2x88x921/(1xe2x88x92zxe2x88x921)n using a z-transformation representing delay of one clock period as zxe2x88x921, and
wherein a transfer function of the feedback circuit is expressed by ((1xe2x88x92zxe2x88x921)nxe2x88x921)/zxe2x88x921 using the z-transformation.
In the above-mentioned frequency synthesizer apparatus, the plural-n-th-order integrator preferably comprises a plurality of n first-order integrators which are cascade-connected,
wherein each of the first-order integrators comprises a second adder and a one-clock delay circuit,
wherein the second adder adds data inputted to each of the first-order integrators to output data from the one-clock delay circuit, and outputs resultant addition data,
wherein the one-clock delay circuit delays the output data from the second adder by one clock period, and outputs the delayed data, and
wherein one of the plurality of n first-order integrators outputs the output data from the one-clock delay circuit of the first-order integrator to the first-order integrator of the following stage, whereas the other first-order integrators output the output data from the second adder to the first-order integrators of each following stage, respectively.
In the above-mentioned frequency synthesizer apparatus, the one-clock delay circuit of a first stage among the plurality of n first-order integrators preferably operates using a first clock,
wherein at least one of the one-clock delay circuits of a second stage and stages following to the second stage among the plurality of n first-order integrators operates using a second clock, and
wherein a period of the first clock is substantially equal to that of the second clock, and a leading edge or trailing edge of the first clock is substantially different from that of the second clock.
In the above-mentioned frequency synthesizer apparatus, each of the cascade-connected first-order integrators is preferably a binary logic circuit, and
wherein a bit length of at least one of the first-order integrators of a second stage and stages following to the second stage is smaller than that of the first-order integrators of a first stage.
In the above-mentioned frequency synthesizer apparatus, the plural-n-th-order integrator preferably comprises:
a second adder;
a one-clock delay circuit; and
a composite delay circuit having a transfer function which is expressed by (1xe2x88x92(1xe2x88x92zxe2x88x921)n)/zxe2x88x921 using a z-transformation representing delay of one clock period as zxe2x88x921, and
wherein the second adder adds data inputted to the plural-n-th-order integrator, to output data from the composite delay circuit, outputs resultant addition data to the composite delay circuit through the one-clock delay circuit, and outputs output data from the one-clock delay circuit as output data from the plural-n-th-order integrator.
In the above-mentioned frequency synthesizer apparatus, the fraction part control circuit preferably comprises:
a first delta-sigma modulator circuit;
a second delta-sigma modulator circuit; and
a natural-number-n-th-order differential circuit having a transfer function which is expressed by (1xe2x88x92zxe2x88x921)n using a z-transformation for representing delay of one clock period as zxe2x88x921,
wherein the first delta-sigma modulator circuit comprises:
a first integrator which is a natural-number-n-th-order integrator;
a first quantizer; and
a first feedback circuit, wherein the second delta-sigma modulator circuit comprises:
a second integrator which is a natural-number-m-th-order integrator;
a second quantizer; and
a second feedback circuit,
wherein output data from the second quantizer of the second delta-sigma modulator circuit is inputted to the natural-number-n-th-order differential circuit,
wherein the fraction part control circuit further comprises:
a second multiplier for multiplying output data from the first quantizer by a predetermined quantization step, and for outputting resultant multiplication data;
a first subtracter for subtracting the output data from the second multiplier from output data from the first integrator, and outputting resultant subtraction data to the second delta-sigma modulator circuit;
a delay for delaying the output data from the first quantizer of the first delta-sigma modulator circuit so as to be synchronized with a timing of output data from the natural-number-n-th-order differential circuit; and
further adder means for adding the output data delayed by the delay to the output data from the natural-number-n-th-order differential circuit, and for outputting resultant addition data as output data from the fraction part control circuit, and
wherein the fraction part control circuit operates as a plural-(n+m)-th-order delta-sigma modulator circuit.
In the above-mentioned frequency synthesizer apparatus, the first delta-sigma modulator circuit preferably operates using a first clock,
wherein the second delta-sigma modulator circuit operates using a second clock, and
wherein a period of the first clock is substantially equal to that of the second clock, and a leading or a trailing timing of the first clock is substantially different from that of the second clock.
In the above-mentioned frequency synthesizer apparatus, the first clock is preferably generated from one of the input reference signal and the output from the variable frequency divider, and the second clock is generated from another one thereof.
In the above-mentioned frequency synthesizer apparatus, the fraction part control circuit is preferably a binary logic circuit,
wherein a bit length indicating data less than the quantization step of the second quantizer in the output data from the second integrator is smaller than that indicating data less than the quantization step of the first quantizer in the output data from the first integrator.
In the above-mentioned frequency synthesizer apparatus, data having a number of bits indicating data less than the predetermined quantization step, which are selected among the output data from the one-clock delay circuit of each of the plurality of n cascade-connected first-order integrators, preferably are sequentially set so as to be equal to or less than the number of bits of the previous stages.
According to another aspect of the present invention, there is provided a communication apparatus comprising:
the above-mentioned frequency synthesizer apparatus;
a transmitting circuit; and
a receiving circuit,
wherein an output signal from the voltage control oscillator, which is an output signal from the frequency synthesizer apparatus, is supplied to the transmitting circuit and the receiving circuit as a local oscillation signal,
wherein the transmitting circuit transmits a radio signal via a frequency channel corresponding to a frequency of the local oscillation signal, and
wherein the receiving circuit receives a further radio signal via a further frequency channel corresponding to the frequency of the local oscillation signal.
According to a further aspect of the present invention, there is provided a frequency modulator apparatus comprising:
the above-mentioned frequency synthesizer apparatus; and
a third adder for adding the input data of the fraction part to input modulation data, and for outputting resultant addition data to the fraction part control circuit, thereby frequency-modulating an output signal from the voltage control oscillator of the frequency synthesizer apparatus in accordance with the modulation data.
According to a still further aspect of the present invention, there is provided a frequency modulating method using a frequency synthesizer apparatus, including the step of:
adding the input data of the fraction part to input modulation data, and outputting resultant addition data to the fraction part control circuit, thereby frequency-modulating an output signal from the voltage control oscillator of the frequency synthesizer apparatus in accordance with the modulation data.
Accordingly, according to the present invention, a higher-order delta-sigma modulator circuit is used, and this leads to the present invention having a unique, advantageous effect of being capable of setting the output frequency at frequency intervals shorter than the reference frequency, and being capable of obtaining an output signal by remarkably reducing undesired spurious components.